The present invention relates to an information processing device and an information processing method and, for example, is preferably used in a central processing unit (CPU) having heterogeneous (asymmetric) multi-cores whose architectures are different from each other.
A device driven on a battery such as a sensor device is required to operate for a long period after being installed without replacing a battery. In such a device, usually, data collection of a sensor is performed by an intermittent operation, and a calculating process using stored data or a data transfer using a network is performed at a certain timing. Since the computing power of the CPU is unnecessary in normal times in which a simple data collecting process is intermittently performed, the CPU may operate at an operation frequency as low as possible so as not to consume power. On the other hand, at the time of performing analysis of a large amount of data or a network process, the process has to be completed in short time at high CPU capability.
To such a request, a technique generally called DVFS (Dynamic Voltage and Frequency Scaling) of changing the operation frequency and voltage of a CPU core in accordance with necessary computing power is used. However, in the architecture of a single CPU core, it is difficult to obtain a characteristic satisfying both low-power consumption and high performance.
ARM Holdings plc (ARM) attempts to solve the problem by big.LITTLE processing architecture which combines a CPU core having a low-power-oriented characteristic and a high-performance CPU core and seamlessly switches software between the cores (refer to Peter Greenhalgh, “Big.LITTLE processing with ARM Cortex™-A15 & Cortex-A7”, ARM, WHITEPAPER, September 2011 (non-patent literature 1)).
A method equivalent to the big.LITTLE architecture of ARM is described in Japanese Unexamined Patent Application Publication (translation of PCT Application) No. 2010-538371 (patent literature 1). The literature discloses a method of transparently switching an application from the OS (Operating System) between two asymmetric cores having characteristics of different operation frequencies and operation power levels. In the configuration of the patent literature, instruction set architectures (ISA) of two asymmetric cores have to have compatibility.